Programmable integrated circuits are known in the art and include programmable logic devices ("PLDs"), Programmable Array Logic ("PALs"), and Programmable Logic Arrays ("PLAs"). Each of these programmable circuits provides an input AND logic plane followed by an OR logic plane. An output function can thus be calculated which is the sum of the products of the input terms. The logic planes are usually programmable such that the initial general layout of the planes may be customized for a particular application.
A more general approach to programmable circuits involves providing an array of distinct, uncommitted logic cells in a Programmable Gate Array ("PGA"). A programmable interconnect network is provided to interconnect the cells, and to provide data input to, and output from, the array. Customization or programming of the otherwise generally-designed logic cells and interconnect network is performed for a particular application. One such array is a Mask Programmable Gate Array ("MPGA"), wherein the configuration of the cells and the wiring network occurs when adding the final layers of metallization to an integrated circuit. A modified approach involves the use of laser-directed energy to customize the metallization pattern. Another such array is a Field Programmable Gate Array ("FPGA"), wherein the configuration can be performed by a user, in the "field." Such configuration may be effected by using electrically programmable fusible links, antifuses, memory-controlled transistors, floating-gate transistors, or the like. The cells of a PGA can be any type of known logic cells, including AND/OR macrocells as in PALs or PLAs.
Each logic cell of an array often includes combinatorial and sequential logic stages. In one common implementation, a cell sequential stage is cascaded with a cell combinatorial stage. The combinatorial stage performs logic functions on cell inputs, and the sequential stage is used to store and output the result. The sequential stages of the logic cells (e.g., flip-flops) often require, in addition to data inputs and outputs, clock and reset signals for proper operation.
In many prior approaches, a single clock and a single reset signal are applied to respective input pads of the array and are internally routed to each sequential stage of the array. The user programmed designs employing these arrays are therefore constrained to single clock and reset implementations. Each portion of the array, even if logically partitioned from the other portions, is nevertheless required to conform to an array-wide clock and reset strategy. The likelihood of logically partitioned arrays increases with advances in semiconductor technology which allow increased logic cell density.
Additionally, because the densities and clock speeds of programmable arrays are increasing with advances in semiconductor technology, array-wide timing tolerances are decreasing. The propagation delay associated with clock or reset signals routed from a signal source (e.g., a chip pad) to a logic cell varies in proportion to the distance between the logic cell and the clock or reset signal source. Since the logic cells are necessarily distributed over the available substrate area in an array, the distances between the logic cells and the clock or reset signal source will vary. This variance causes skew between the signals routed to logic cells which may be outside of the timing tolerances of dense, high-speed arrays.
What is needed, therefore, is a flexible clock and reset distribution architecture which overcomes the limitations of the array-wide designs of the prior approaches, and which employs techniques to minimize the clock and reset signal skew across the array.